The present invention relates to a MIS integrated circuit, as well as to its manufacturing process. It more particularly applies in the field of the manufacture of integrated memory circuits of the MOS or CMOS type and more particularly to non-volatile memories of the EPROM, EEPROM and ROM type.
An integrated memory is an integrated circuit incorporating the actual memory part, called the memory cell, which is formed from several electrically interconnected memory points and peripheral circuits used for controlling the memory points. The invention relates solely to the actual memory part and to its manufacture.
The most modern floating grid or gate EPROM memory cells make it possible to store 10.sup.6 bits, which now have surfaces of 20 to 25 .mu.m.sup.2 in a 1.2 .mu.m technology, i.e. in which the smallest strips and spaces are 1.2 .mu.m. Thus, the surface of a memory is approximately 14 to 17 times the elementary lithography square (1200.times.1200 nm.sup.2.
FIG. 1 diagrammatically shows in perspective a known floating gate EPROM memory cell. As shown in FIG. 1, a memory point is formed from a transistor having a source 4 and a drain 6 produced in a monocrystalline silicon semiconductor substrate 8. The source and drain have reverse conductivities to those of the substrate.
The transistor also comprises a gate insulant 10, generally of silicon dioxide, on which are stacked a first gate 12 and a second gate 14, which are generally made from phosphorus-doped polycrystalline silicon. These two gates are separated by a fine insulant layer 16, which is generally of silicon dioxide. The first gate 12 is a floating gate and the second gate 14 the control gate of the memory point. This memory point is electrically insulated, by means a field oxide 18 produced by local surface oxidation of the substrate, from the other memory points, as well as peripheral control circuits of said memory point.
The complete memory cell is covered with a thick insulating layer 22, which is generally of silicon dioxide, in which are formed the electric contact holes for the sources and drains, such as 24. The electrical connections between these sources and drains of the different memory points and/or the different peripheral control circuits are realised by a conductive layer 26, which is generally of aluminium and which is deposited on insulating layer 24 and etched in appropriate manner.
The electrical connections between the control gates of the different memory points are defined at the same time as the control gates 14 and in the same polycrystalline silicon layer. They are consequently located below the interconnections for the sources and the interconnections for the drains.
Increasing attempts are being made to reduce the size of integrated circuits and in particular memories with a view to increasing their integration density. Unfortunately in the presently known EPROM memories two factors limit the reduction of the dimensions of such a memory cell.
The first factor is the projection 28 of the floating gate 12 above the field oxide 18. This projection is necessary due to the superimposing imprecision of the different layers constituting the memory points and lithography masks necessary for etching the different layers. This projection is in direction X of the lines of words (for connections of gates) of the memory cell, said direction being perpendicular to those of the channels of the memory points. In MIS circuits, the projection of the single gate of the transistors also occurs above the field oxide.
The second factor, which is in direction Y of the lines of bits and parallel to the direction of the channels of the memory points, is the need to provide insulating guards 30 around the contact holes of the bit line, i.e. around the contact holes of the drains of the memory points. This second limiting factor also exists in EEPROM and ROM memories and in general terms in any MIS integrated circuit.
In particular, in integrated circuits with polycrystalline silicon control gates, the drains and sources of the components are auto-positioned with respect to the gate as a result of an ion implantation using the gates as a mask. Thus, any intersection of a polycrystalline silicon strip and an active zone or doped zone of the substrate produces a MIS transistor. It is also not possible to intersect a "diffused" strip (n+ or p+) in the substrate acting as a connection for the sources and drains with a connection of the polycrystalline silicon gates.
In order to effect such intersections, it is necessary to use an insulating layer and a layer of metal conductor lines on said insulating layer, which takes up a large amount of space due to the need for bringing about contacts within said layer. Moreover, "diffused" strips in the substrate cannot in themselves constitute interconnection lines as a result of their high resistivity.
The reduction to the lithographic dimensions are not generally accompanied by a proportional improvement in the superimposing precisions of the different levels, particularly lithographic masking levels, so that the limiting factors referred to hereinbefore become increasingly disadvantageous for an increase in the integration density, especially of non-volatile memories.
Auto-alignment or auto-positioning processes avoiding the projection of the floating gate over the field oxide and/or insulating guards around the contact holes are consequently necessary for future generations of non-volatile memories.
Apart from integration density problems, the presently known non-volatile memories and EPROMs require, during programming corresponding to writing, the application of high voltages to the memory point control gate of approximately 12.5 V, in order to inject hot electrons, produced close to the drain, into the floating gate. The use of such high programming voltages is consequently a constraint for the design of peripheral circuits for controlling the memory cell.